Principal Logic Design Engineer

Intel; Toronto; Hybrid; CAD 100,000 - 125,000; Full time

Job summary

A leading technology company in Toronto is seeking an experienced Principal Logic Design Engineer. This role involves logic design, RTL coding, and defining architecture for next-generation products. The ideal candidate will have a strong background in High-Speed SerDes design, excellent communication skills, and a collaborative mindset. You will participate in optimizing designs while ensuring quality integration and verification of SoC components. The position allows for a hybrid work model, balancing remote and onsite work.

Qualifications

• 10+ years of experience or 6+ years with a Master's degree.
• Deep experience in High-Speed SerDes design.

Responsibilities

• Logic design and RTL coding for IP and subsystems.
• Define architecture and microarchitecture features.
• Optimize logic to meet power and performance goals.
• Review verification plans and implementation.
• Support SoC customers with quality integration.

Skills

Mixed-signal design

High-Speed SerDes design and architecture

Post-silicon validation

Scripting proficiency (TCL, Perl, Python, Ruby)

Excellent communication

Excellent teamwork

Education

Bachelor’s in electrical/computer engineering

Master’s degree

Job description

Job Details: Job Description:

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.

About the Role

Intel's multiprotocol SerDes design team is hiring in our Toronto office to ensure continued support of some of the world's most versatile next‑generation products. We have a long track record of silicon success over multiple technology nodes. Supporting the team in Toronto, we are hiring a technically experienced Principal Logic Design Engineer.

The key responsibilities of this person include the following:

• Logic design, register transfer level (RTL) coding, analog circuit behavioral modeling and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Participating in the definition of architecture and microarchitecture features of the block being designed.
• Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supporting SoC customers to ensure high quality integration and verification of the IP block.
• Driving quality assurance compliance for smooth IP SoC handoff.
• Create design documentation

The Logic Design Engineer should possess the following attributes:

• Excellent communication: Expected to drive clarity across partners, managers.
• Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can.
• Strong analytical and problem‑solving skills with the skills to independently draw conclusions.

Required Skills and Experience:

• Mixed‑signal design, specifically High‑Speed SerDes design and architecture
• Experience with PCS/FEC, gearbox, equalization, and clocking structures
• Experience with pipelining, retiming, clock domain crossings (CDC), and latency optimization
• Experience with post‑silicon validation and support of High‑Speed SerDes IP
• Experience working with automated Place‑and‑Route (APR) teamson synthesis, STA constraints, timing closure, and DFT considerations
• Knowledge of FFE/DFE filters, CDR DSP blocks, interpolation/decimation, and adaptive algorithms
• Reading and interpreting technical specifications to develop microarchitecture and implement RTL design in SystemVerilog
• Excellent communication: Expected to drive clarity across partners, managers.
• Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can

Preferred Skills and Experience:

• Familiarity with AXI, AHB, and APB protocols
• DSP‑based CDR design, Forward Error Correction (FEC) coding, hardware/software co‑simulation, power/performance optimization, and machine learning‑assisted DSP tuning
• Experience with PCIe, Ethernet (100G/400G/800G), CEI, USB, or similar standards
• Scripting proficiency in at least one interpreted language (e.g., TCL, Perl, Python, Ruby)
• Knowledge of UVM/testbench architecture, constrained random testing, and functional coverage

Qualifications:

• Bachelor’s in electrical/computer engineering and 10+ years of experience -OR- Master’s degree with 6+ years of experience
• Deep experience in Mixed signal design specifically High Speed SerDes design and architecture

Job Type: Experienced Hire Shift: Shift 1 (Canada) Primary Location: Canada, Toronto Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

Canada Accommodation

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Annual Salary Range for jobs which could be performed in Canada

Salary range dependent on a number of factors including location and experience.