Principal Engineer - CAD Physical Verification

Microchip Technology Inc.; Burnaby; On-site; CAD 119,000 - 258,000; Full time

Job summary

A global technology company is looking for a Principal Engineer in CAD Physical Verification in Burnaby, Canada. The role requires expertise in physical verification and tools like Siemens Calibre and Cadence Pegasus. Candidates should have 8+ years of experience and strong programming skills in Tcl/Tk, Perl, and Python. The position offers a salary range of $86,000 - $186,000, along with comprehensive benefits from day one.

Benefits

Health benefits from day one

Retirement plans

Stock options

Qualifications

• 8+ years in physical verification activities.
• Deep knowledge of Calibre DesignRev scripting, SVRF, and TVF.
• Experience debugging PV issues with RVE, Vue, or similar visualizers.

Responsibilities

• Develop physical verification regression test cases.
• Support Layout and Design engineers with physical verification.
• Collaborate to develop DRC rules and manufacturability checks.

Skills

Siemens Calibre

Cadence Pegasus

Tcl/Tk

Perl

Python

debugging

Tools

Calibre DesignRev

Cadence Virtuoso

Synopsys Hercules

Job description

Principal Engineer - CAD Physical Verification

Join Microchip Technology Inc. as a Principal Engineer in CAD Physical Verification.

Job Description

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development, providing innovative solutions for the design community. The candidate will focus on flow development and support for back-end physical verification, requiring a solid software background and interest in supporting semiconductor chip design.

Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS, and PERC tools is essential. The candidate should know how to run tools, debug results, develop verification run decks, and automate flows and procedures.

An understanding of both digital and analog design is important, as development and support work will span various design styles. Knowledge in circuit/electrical and layout/physical design is also required.

Responsibilities

• Develop physical verification regression test cases to QA verification decks.
• Support Layout and Design engineers with physical verification activities using Siemens Calibre, Cadence Pegasus, or Synopsys Hercules.
• Utilize advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling, etc.
• Collaborate with Technology Development and Device Engineering to develop DRC rules, additional devices, and manufacturability checks.
• Develop and verify rule decks to support flows.
• Support remote sites worldwide with layout verification activities.
• Debug physical verification issues.
• Contribute to team efforts to develop flows that improve device quality and reliability.

Additional tasks based on experience may include building regression test cases for various PDKs, supporting PDKs from TSMC, Global Foundries, and others, and setting up PERC for several PDKs.

Qualifications

• 8+ years in physical verification activities.
• Deep knowledge of Calibre DesignRev scripting, SVRF, and TVF.
• Experience debugging PV issues with RVE, Vue, or similar visualizers.
• Proficiency in Tcl/Tk, Perl, Python, and other programming languages.
• Strong understanding of layout rules, device identification, and foundry rules.
• Knowledge of Design for Manufacturing solutions.
• Prefer extensive knowledge of Calibre/ Pegasus/ Hercules syntax and semantics.
• Familiarity with Cadence Virtuoso and CalibreDRV.
• Optional: Extraction, Reliability, Dynamic Noise knowledge.
• Excellent communication skills.

Additional Details

Travel: 0%-25%

Salary Range: $86,000 - $186,000, depending on experience and location.

Microchip offers comprehensive benefits, including health benefits from day one, retirement plans, and stock options.

We are committed to accessibility and accommodate applicants with disabilities throughout the hiring process.

This job posting is active and not expired.