Lead Digital Verification Engineer

Cadence; Toronto; On-site; CAD 85,000 - 110,000; Full time

Job summary

A leading technology firm is seeking a Lead Verification Engineer in Toronto to ensure high-quality digital RTL verification and develop reusable verification components. The successful candidate will contribute to various verification activities and must possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science. Familiarity with SystemVerilog, UVM, and scripting languages is preferred. The role involves collaboration across teams and requires full-time presence in the Toronto office, with minimal travel expectations.

Qualifications

• Bachelor's degree in engineering or computer science is required.
• Experience with UVM and digital design flow is essential.
• Familiarity with various communication protocols is a plus.

Responsibilities

• Verify digital RTL and develop reusable verification components.
• Contribute to verification flows, test planning, and execution.
• Collaborate effectively with design and verification teams.

Skills

Understanding of verification architecture and methodologies

Understanding of Metric Driven Verification

Understanding of Universal Verification Methodologies (UVM)

Understanding of functional coverage planning and checks

Understanding of SystemVerilog Assertions (SVAs)

Understanding of digital design flow

Experience with scripting languages (Python, Perl, Ruby, Sed, Awk)

Education

Bachelor of Science in Electrical Engineering, Computer Engineering, or Computer Science

Master of Science in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence tools

Job description

Overview

Lead Verification Engineer role at Cadence in Montreal, Ottawa, Toronto. The successful candidate will join a dynamic team developing high-performance IP for industry-standard protocols. The role requires a self-motivated individual who can work independently to complete tasks within project timelines with high quality.

The candidate will primarily be responsible for the verification of digital RTL and the development of reusable verification components and environments. The role also involves contributing to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure. Strong communication of project progress to all technical staff is essential.

The ideal candidate will understand the end-to-end verification flow and be able to collaborate effectively with design teams, verification teams, project management, and digital/analog design teams across multiple geographies. Willingness to work full time in the Montreal, Quebec, Canada office and travel as required by the job function (expectation is 5% travel or less).

Cadence’s IP Design group is growing; the complete IP portfolio can be found at the Cadence IP portfolio overview.

Responsibilities (summary)

The candidate will verify digital RTL and develop reusable verification components and environments. They will contribute to verification flows, test planning and execution, and closure activities for functional and code coverage. They will communicate progress to the technical staff and collaborate with cross-functional teams across locations.

Minimum Experience

• Bachelor of Science in Electrical Engineering, Computer Engineering, or Computer Science


• Understanding of verification architecture and methodologies


• Understanding of Metric Driven Verification


• Understanding of Universal Verification Methodologies (UVM)


• Understanding of functional coverage planning and checks


• Understanding of SystemVerilog Assertions (SVAs)


• Understanding of digital design flow

Preferred Experience

• Master of Science in Electrical Engineering, Computer Engineering, or Computer Science


• Experience with SystemVerilog UVM coding


• Experience with scripting languages (Python, Perl, Ruby, Sed, Awk)


• Exposure to protocols such as PCIe, USB, SATA, Ethernet, DisplayPort, HDMI


• Exposure to Formal Verification Technologies


• Exposure to Mixed‑Signal Design


• Experience with Cadence tools

Exposure to Low Power verification using CPF or UPF

Cadence is an equal‑opportunity employer committed to hiring a diverse workforce.

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