Application Engineer I Digital Verification & Simulation VIP

Cadence Systems; Belo Horizonte; Presencial; BRL 120.000 - 160.000; Tempo integral

Resumo da oferta

A leading technology firm in Belo Horizonte is seeking a motivated Application Engineer I specializing in Digital Verification and Simulation. The successful candidate will be trained to become an expert in verification methodologies while providing technical support to customers. Candidates must have a degree in engineering or related fields, with proficiency in Portuguese and English. The role involves collaborating with R&D and engaging with customers to ensure product success. Competitive benefits are offered.

Serviços

Competitive benefits

Qualificações

• Excellent verbal and written communications skills in Portuguese and English.
• Good problem-solving skills.
• Strong inter-personal and communication skills.
• A strong interest in debug and contributing to customer success.

Responsabilidades

• Provide technical support in RTL verification solutions.
• Contribute to technical and sales meetings.
• Develop and run cases to verify problems.
• Collaborate with R&D on technical issues.
• Engage with the AE team on technical campaigns.

Conhecimentos

Verilog

VHDL

TCL

Python

Problem-solving

Communication skills

Formação académica

Bachelors in Electrical Engineering

Bachelors in Computer Engineering

Bachelors in Electronics Engineering

Bachelors in Control and Automation Engineering

Bachelors in Computer Science

Bachelors in Information Systems

Bachelors in Computational Mathematics

Ferramentas

Cadence verification tools

Descrição da oferta de emprego

Overview

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer I : Digital Verification & Simulation - VIP to work with us in Belo Horizonte Brazil.

As an Application Engineer you will be trained to become an expert in Digital Verification & Simulation methodologies in the System Verification Group - Technical Field Operations (TFO-SVG) in Belo Horizonte. The TFO-SVG group works with Xcelium Palladium Protium Jasper VIPs Perspec and other Cadence Digital Functional Verification tools.

The application engineers provide technical support enabling customers to effectively deploy our industry-leading technology focused on RTL-level verification products. You will be in a Digital Verification & Simulation focused team working with our Verification IP Solutions complimentary tools and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success coming up with innovative solutions to address the industrys most challenging problems.

Responsibilities

• Activities focused on the Functional Verification field as mentioned above reporting to higher management.
• Provide technical support in engagements with customers and field personnel in RTL verification solutions focused on the Cadence Verification IP solutions and other supporting technologies.
• Contribute to technical and sales meetings interacting with engineers technical leads and executives.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Develop and run cases to verify problems create workarounds test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.
• Author application notes and help provide feedback on documentation.
• Use scripting languages like TCL and Python for flow development automation and enhancing design methodologies.
• Engage with AE team on pre-sales and post-sales technical campaigns from the technical side working along with Sales and Marketing to plan deployment conduct technical evaluations and support.

Requirements

• Complete bachelors in Electrical Engineering Computer Engineering Electronics Engineering Control and Automation Engineering Systems Engineering Computer Science Information Systems Computational Mathematics or related areas.
• Excellent verbal and written communications skills in Portuguese and English.
• Good problem-solving skills.
• Strong inter-personal and communication skills.
• A strong interest in debug and contributing to customer success with related technical interest in EDA hardware development (HDLs) Logic Design / Verification and the semiconductor industry.

Nice to have

• Exposure to RTL (Verilog or VHDL).
• Knowledge of verification methodologies such as UVM is a plus.
• Knowledge of industry standard protocols such as AMBA USB Ethernet etc. is a plus.
• Knowledge of memory models is a plus.
• Experience in scripting languages such as TCL and Python is a plus.
• Exposure to microelectronics semiconductors and or EDA with experience on functional verification (simulation) model verification or Verification IP.
• Knowledge of Cadence verification tools is a plus.

Additional Job Details

• Employment category : CLT.
• Employment term : 40 hours / week.
• Competitive benefits.
• Av. do Contorno 5800 Savassi Belo Horizonte Minas Gerais Brazil

About Cadence Design Systems

At Cadence we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Cadence is the only company that provides the expertise and tools IP and hardware required for the entire electronics design chain from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live work and play. Our products are used in mobile consumer cloud datacenter automotive aerospace IoT industrial and other market segments. For more information access .

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