TPU RTL Design Engineer for AI Hardware Acceleration

Google

Sunnyvale (CA)

On-site

USD 163,000 - 236,000

Full time

4 days ago

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Job summary

Google is shaping the future of AI/ML hardware acceleration with a focus on TPU architecture and its integration into AI/ML systems. This role involves SoC RTL design for data center accelerators, including management and control subsystems, clocking, reset, and chip management.

You will collaborate across software, hardware, and architecture teams to deliver cutting-edge digital designs. Join a team driving Google's TPU progression and global hyperscale computing, contributing to RTL

Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
Experience with scripting languages.

Responsibilities

Learn more about benefits at Google.
Work separately to create and review management and control subsystem's design microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with architecture and power teams to evaluate features and their impact.
Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.