TPU RTL Design Engineer for ML Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 198,000; Full time

Job summary

Google is seeking an RTL Design Engineer for the TPU team in Sunnyvale, CA to shape next‑gen AI accelerators. You will design and verify microarchitecture and RTL in SystemVerilog, collaborating with DV, PD, and firmware to deliver high‑quality hardware.

The role focuses on On‑Chip Network and integration of TPU blocks, with opportunities to optimize timing, area, and power while contributing to cross‑functional design flows and post‑silicon support.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing‑critical RTL development.
• Design experience optimizing for performance, power, and area.
• Experience with digital design fundamentals and microarchitecture design.
• Experience working cross‑functionally with DV and PD teams.

Responsibilities

• Define and document complex microarchitecture for the TPU, writing high‑quality, performant, and power‑efficient RTL code primarily in SystemVerilog.
• Partner with cross‑functional teams to drive block‑level and chip‑level integration efforts for the machine learning accelerators.
• Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness.
• Support post‑silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies.
• Work closely with the physical design team to meet timing, area, power, and manufacturability requirements.

Skills

RTL design

SystemVerilog

ASIC design

Cross‑functional collaboration

Performance/power/area optimization

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD preferred

Tools

Linting

CDC

RDC

LEC

Job description

Google is seeking an RTL Design Engineer for the TPU team in Sunnyvale, CA to shape next‑gen AI accelerators. You will design and verify microarchitecture and RTL in SystemVerilog, collaborating with DV, PD, and firmware to deliver high‑quality hardware.

The role focuses on On‑Chip Network and integration of TPU blocks, with opportunities to optimize timing, area, and power while contributing to cross‑functional design flows and post‑silicon support.