TPU Compute RTL Design Engineer - AI Hardware Innovator

Google Inc.; Austin (TX); Hybrid; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is shaping the future of AI/ML hardware acceleration by developing TPU technology and custom silicon solutions. You will contribute design and verification expertise focused on TPU architecture within AI/ML systems, collaborating across software, architecture, and cross-functional teams.

The role emphasizes driving innovation in cutting-edge hardware, with opportunities to influence compute subsystems and integration in hyperscale environments, while engaging with teams worldwide.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent practical experience).
• 4 years of experience with digital design using SystemVerilog RTL.
• Experience with Computer Architecture.

Responsibilities

• Develop SystemVerilog RTL to implement ASIC logic per guidelines.
• Work with DV teams to create testplans and verify RTL.
• Collaborate with physical design to ensure timing closure and physical requirements.
• Review compute subsystem design microarchitecture specifications.

Skills

SystemVerilog RTL

Digital design

Computer Architecture

Mentoring

Education

Bachelor's degree (EE/CE/CS) or equivalent

Job description

Google is shaping the future of AI/ML hardware acceleration by developing TPU technology and custom silicon solutions. You will contribute design and verification expertise focused on TPU architecture within AI/ML systems, collaborating across software, architecture, and cross-functional teams.

The role emphasizes driving innovation in cutting-edge hardware, with opportunities to influence compute subsystems and integration in hyperscale environments, while engaging with teams worldwide.