TPU RTL Design Engineer – AI Hardware Interconnect + Equity

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Inc. in Sunnyvale, CA is seeking a Share TPU RTL Design Engineer focused on inter-chip interconnects and AI hardware acceleration. You will design RTL IP for high-speed interconnect subsystems and contribute to TPU architecture and its integration in AI systems.

The role involves project definition, RTL design, verification, and collaboration with multiple teams to deliver data-center accelerators powering Google's AI workloads.

Qualifications

• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across MAC, L2, or PHY layers.
• Experience with high-speed interconnects.
• Preferred: Master’s or PhD focusing on computer architecture.

Responsibilities

• Verify complex digital designs with focus on TPU architecture and integration.
• Design RTL IP for chip-to-chip high-speed interconnect subsystems.
• Participate in project definition, RTL design, and implementation.
• Collaborate with Verification and Physical Design teams to meet timing, area, and power targets.
• Contribute to data center accelerator development and AI hardware.

Skills

RTL design

ASIC design

Networking IP

Interconnects

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture

Tools

SystemVerilog

Job description

Google Inc. in Sunnyvale, CA is seeking a Share TPU RTL Design Engineer focused on inter-chip interconnects and AI hardware acceleration. You will design RTL IP for high-speed interconnect subsystems and contribute to TPU architecture and its integration in AI systems.

The role involves project definition, RTL design, verification, and collaboration with multiple teams to deliver data-center accelerators powering Google's AI workloads.