TPU Compute RTL Design Engineer for AI Hardware

Google; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is seeking an experienced hardware engineer to shape the future of AI/ML hardware acceleration and drive TPU technology powering Google's AI/ML applications. You will verify complex digital designs, focusing on TPU architecture and its integration within AI/ML systems, collaborating with software and cross‑functional teams to deliver high‑performant, scalable silicon used across Google services.

This role offers the chance to work on hyperscale hardware, contribute to industry-leading

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS
• 4 years of digital design experience with SystemVerilog RTL
• Experience with Computer Architecture

Responsibilities

• Create and review Compute subsystem design microarchitecture specifications.
• Develop SystemVerilog RTL to implement ASIC logic per guidelines.
• Collaborate with DV teams to create test plans, verify and debug RTL.
• Coordinate with physical design teams to meet timing and physical constraints.

Skills

SystemVerilog RTL

Computer Architecture

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

Google is seeking an experienced hardware engineer to shape the future of AI/ML hardware acceleration and drive TPU technology powering Google's AI/ML applications. You will verify complex digital designs, focusing on TPU architecture and its integration within AI/ML systems, collaborating with software and cross‑functional teams to deliver high‑performant, scalable silicon used across Google services.

This role offers the chance to work on hyperscale hardware, contribute to industry-leading