TPU SoC Design Engineer: AI Hardware Accelerator

Google; Town of Montana (WI); On-site; USD 116,000 - 165,000; Full time

Job summary

Google's TPU SoC Design Engineer role in Sunnyvale, CA invites you to shape AI/ML hardware acceleration. You will lead digital RTL design for TPU architecture, developing top-level RTL, architecture, and interconnects for data-center accelerators within a cross-functional team.

The role involves collaboration with Verification, Physical Design, and Firmware teams, focusing on efficient design environments, tool flows, and scalable IP.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write RTL code in SystemVerilog, focusing on performance and power efficiency.
• Collaborate with Verification to develop test plans, debug RTL, ensure functional correctness.
• Work with Physical Design to meet timing, area, power, manufacturability requirements.
• Contribute to development of tools, flows, methodologies.

Skills

ASIC RTL design

SystemVerilog/Verilog

digital design

EDA tool experience

Education

Bachelor's degree in Electrical Engineering or related field

Master's or PhD in Electrical/Computer Engineering (preferred)

Tools

Verdi

VCS

Job description

Google's TPU SoC Design Engineer role in Sunnyvale, CA invites you to shape AI/ML hardware acceleration. You will lead digital RTL design for TPU architecture, developing top-level RTL, architecture, and interconnects for data-center accelerators within a cross-functional team.

The role involves collaboration with Verification, Physical Design, and Firmware teams, focusing on efficient design environments, tool flows, and scalable IP.