RTL Design Engineer - AI/TPU SoC/ASIC (Equity)

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is shaping the future of AI/ML hardware acceleration by developing custom silicon solutions that power TPU architecture and AI-driven systems. You will verify complex digital designs and contribute to TPU integration within AI workloads, collaborating across software, architecture, and hardware teams.

The role emphasizes design verification expertise and interaction with cross-functional teams to deliver cutting-edge TPU technology used by Google's products and services worldwide.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
• 4 years of experience with custom silicon design (SoCs, ASICs, etc.).
• Experience with RTL design using Verilog or SystemVerilog.

Responsibilities

• Understand the overall application of the chip, proposing and developing improvements in overall design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on functionality, interfaces, and documentation.

Skills

RTL design (Verilog/SystemVerilog)

Custom silicon experience (SoCs/ASICs)

Education

Bachelor's degree in electrical/computer engineering or related field

Tools

Python

Perl

Job description

Google is shaping the future of AI/ML hardware acceleration by developing custom silicon solutions that power TPU architecture and AI-driven systems. You will verify complex digital designs and contribute to TPU integration within AI workloads, collaborating across software, architecture, and hardware teams.

The role emphasizes design verification expertise and interaction with cross-functional teams to deliver cutting-edge TPU technology used by Google's products and services worldwide.