Senior RTL Design Engineer - TPU AI/ML Accelerators

Google; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

equity

comprehensive benefits

Job summary

Google seeks a Senior RTL Design Engineer in Sunnyvale to drive AI/ML hardware innovation. You'll design RTL IP for TPU technology, contributing to unique solutions for Google's advanced applications.

Expect responsibilities in microarchitecture specifications, SystemVerilog development, and collaboration with design and physical teams. Ideal candidates have a strong ASIC design background and a Bachelor's in a related field.

Compensation includes a competitive salary, bonus, equity, and comprehensive benefits.

Qualifications

• 8 years of experience in ASIC design.
• Experience interacting with cross‑functional teams.
• Understanding of chip management, clocking, reset, and peripherals.

Responsibilities

• Create and review design microarchitecture specifications.
• Develop SystemVerilog RTL for ASIC products.
• Work with design validation teams to create and verify tests.
• Collaborate with architecture and power teams.

Skills

SystemVerilog/RTL coding

Scripting languages (e.g., Tcl, Python, Perl)

ASIC design

Digital design fundamentals

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Google seeks a Senior RTL Design Engineer in Sunnyvale to drive AI/ML hardware innovation. You'll design RTL IP for TPU technology, contributing to unique solutions for Google's advanced applications.

Expect responsibilities in microarchitecture specifications, SystemVerilog development, and collaboration with design and physical teams. Ideal candidates have a strong ASIC design background and a Bachelor's in a related field.

Compensation includes a competitive salary, bonus, equity, and comprehensive benefits.