TPU PCIe Design Lead & RTL Architect

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Inc. Sunnyvale is seeking an experienced PCIe Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and integration.

You will design and verify SoC-level RTL for next-gen data center accelerators, building clocking, reset, error handling, and power management.

Join a collaborative team advancing Google's TPUs, driving silicon bring-up and performance for AI infrastructure.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• 10 years of ASIC design experience, including a PCIe project.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog RTL development and microarchitecture definition.
• Experience with PCIe protocol layers or LTSSM.
• Knowledge of CDC, timing closure, or synthesis flows.

Responsibilities

• Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs meet PPA targets and coding standards.
• Manage the full RTL lifecycle, including documentation and sign-off for Lint, CDC, and synthesis.
• Partner with system architects to meet chip-level bandwidth, latency, and power goals.
• Coordinate with Verification and Physical Design teams to develop test plans, PCIe VIP usage, and timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up for link integrity.

Skills

ASIC design

PCIe protocol expertise

RTL debugging with Verdi/VCS

Python/Perl scripting

SystemVerilog/Verilog RTL

CDC and timing closure

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD preferred

Tools

Verdi

VCS

PCIe VIP

Python/Perl scripting

Job description

Google Inc. Sunnyvale is seeking an experienced PCIe Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and integration.

You will design and verify SoC-level RTL for next-gen data center accelerators, building clocking, reset, error handling, and power management.

Join a collaborative team advancing Google's TPUs, driving silicon bring-up and performance for AI infrastructure.