TPU Hardware Design Engineer for AI/ML Acceleration

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Job summary

Google in Sunnyvale, CA is seeking a mid-level RTL design engineer to shape the TPU microarchitecture and contribute to AI/ML hardware acceleration. You will design high-performance, power-efficient SystemVerilog RTL for complex digital designs and work to optimize for speed, power, and area.

You will collaborate with Verification and Physical Design teams to meet strict timing, area, power, and manufacturability requirements, while supporting post-silicon validation and cross-functional

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Experience in design optimizing for performance, power, and area.

Responsibilities

• Define TPU microarchitecture and develop high-quality, performant SystemVerilog RTL code for complex digital designs.
• Partner with Verification teams to develop test plans, debug RTL, and ensure functional correctness, alongside supporting post-silicon validation efforts.
• Collaborate closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Work seamlessly with internal Partner teams to support and drive critical design integration efforts across the ecosystem.

Skills

RTL design

Digital design

Microarchitecture design

Performance optimization

Education

Bachelor's degree (EE/CS)

Master's or PhD in EE/CE/CS

Tools

SystemVerilog

Python

Perl

ASIC synthesis

Job description

Google in Sunnyvale, CA is seeking a mid-level RTL design engineer to shape the TPU microarchitecture and contribute to AI/ML hardware acceleration. You will design high-performance, power-efficient SystemVerilog RTL for complex digital designs and work to optimize for speed, power, and area.

You will collaborate with Verification and Physical Design teams to meet strict timing, area, power, and manufacturability requirements, while supporting post-silicon validation and cross-functional