Senior SoC Verification Engineer — System-Level Tape-Out

Socket.dev; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Velaura is seeking a senior Design Verification Engineer to verify a next-generation Physical AI SoC. You will lead system-level verification across boot, root of trust, clock/reset topology, low power, and IO/memory subsystems, coordinating with architects, RTL and firmware teams.

Responsibilities include building SoC verification environments for ARM/RISC-V based CPUs, verifying boot flows and security transitions, and ensuring tape-out readiness.

Qualifications

• 10+ years in design verification, with notable SoC level experience.
• Leading or participating in multiple SoC verification projects including sign off and tape out.
• Experience with SystemVerilog, UVM, C/C++ and coverage-driven verification at system level.
• Experience managing simulation flows on CPU-based SoCs such as ARM or RISC‑V.
• Knowledge of IO and memory IP like PCIe and LPDDR5/LPDDR6.
• Experience verifying boot sequences and root of trust.
• Experience with CDC/RDC tools for system-level verification.
• Experience with low power verification tools and UPF based flows.

Responsibilities

• Drive verification planning and execution for assigned areas of the SoC.
• Build and maintain SoC-level simulation environments and flows for CPU-based SoCs (ARM or RISC-V).
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock/reset topology, power domains and low power behavior at system level.
• Verify IO/memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with design teams.
• Verify system-level latency, bandwidth and QoS under representative workloads.
• Support SoC sign-off criteria, coverage closure and tape-out readiness.

Skills

SystemVerilog

UVM

C/C++

SoC verification

ARM/RISC-V

PCIe/ LPDDR

Boot/root of trust

CDC/RDC

Low power verification

Sign-off / Tape-out

Tools

CDC tools

RDC tools

Emulation

FPGA prototyping

Job description

Velaura is seeking a senior Design Verification Engineer to verify a next-generation Physical AI SoC. You will lead system-level verification across boot, root of trust, clock/reset topology, low power, and IO/memory subsystems, coordinating with architects, RTL and firmware teams.

Responsibilities include building SoC verification environments for ARM/RISC-V based CPUs, verifying boot flows and security transitions, and ensuring tape-out readiness.