Lead SoC Verification Architect (System-Level)

Socket.dev; Santa Clara (CA); On-site; USD 210,000 - 270,000; Full time

Job summary

Velaura is seeking an experienced verification leader to drive the SoC verification strategy for the Velaura Physical AI SoC. You will lead a small team, stay hands-on, and work with architects, RTL, firmware, and system teams to ensure correct, reliable performance and safety from RTL blocks to full systems.

You will own the verification plan through sign-off, coordinating boot, security, clock/topology, low power, IO and memory subsystems, and driving coverage to tape-out readiness.

Qualifications

• 12+ years in design verification, with major SoC level exposure.
• Proven track at leading SoC verification across sign-off and tape-out.
• Experience building and leading verification teams.
• Proficient in SystemVerilog, UVM, C/C++, and coverage-driven verification.
• Experience with ARM or RISC-V CPU-based verification and SoC interconnects like PCIe.
• Strong cross-team communication and leadership.

Responsibilities

• Own SoC level verification strategy and plan through tape-out.
• Build and lead a team of verification engineers.
• Define verification architecture and environment; hands-on coding.
• Coordinate verification across boot, security, clocks, power, IO and memory.
• Define sign-off criteria and ensure coverage goals.
• Track progress, coverage, and risk to leadership.
• Collaborate with architecture, RTL, DFT, firmware, and software teams.
• Partner with CAD for simulation, emulation, and regression capacity.

Skills

SystemVerilog

UVM

C/C++

SoC verification

Leadership

ARM/RISC-V

PCIe/LPDDR

CDC/RDC/UPF

Boot/RT verification

Communication

Tools

Emulation

FPGA Prototyping

Simulation Tools

Job description

Velaura is seeking an experienced verification leader to drive the SoC verification strategy for the Velaura Physical AI SoC. You will lead a small team, stay hands-on, and work with architects, RTL, firmware, and system teams to ensure correct, reliable performance and safety from RTL blocks to full systems.

You will own the verification plan through sign-off, coordinating boot, security, clock/topology, low power, IO and memory subsystems, and driving coverage to tape-out readiness.