Senior SoC SystemVerilog Verification Engineer

Velaura AI, Inc.; Santa Clara (CA); Hybrid; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking an experienced Design Verification Engineer focusing on system-level verification for its Physical AI SoC. You will verify boot flows, security state transitions, and IO/memory subsystems across typical workloads.

The role requires leadership in verification projects and hands-on experience with CDC/RDC tools, low power flows, and emulation or FPGA prototyping to accelerate tape-out readiness.

Qualifications

• 10+ years in design verification with significant SoC level experience.
• Experience leading or participating in multiple SoC verification projects including sign off and tape out.
• Proficient with SystemVerilog, UVM, C and C++ and coverage-driven verification at system level.
• Experience managing simulation flows on CPU-based SoCs such as ARM or RISC-V.
• Knowledge of PCIe and LPDDR5/LPDDR6 IO/memory subsystems.
• Experience verifying boot flows and root of trust.

Responsibilities

• Drive verification planning and execution for assigned areas of the Velaura Physical AI SoC.
• Build and maintain SoC level simulation environments and flows for CPU-based SoCs such as ARM or RISC-V.
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock and reset topology, power domains and low power behavior at system level.
• Verify IO and memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with the design teams.
• Verify system level latency, bandwidth and QoS under representative workloads.
• Support SoC sign off criteria, coverage closure and tape out readiness.

Skills

SystemVerilog/UVM

C/C++

SoC verification

Boot sequences

Root of trust

Clock/Reset topology

Low power verification

Tools

Emulation

FPGA prototyping

CDC/RDC tools

Job description

Velaura AI, Inc. is seeking an experienced Design Verification Engineer focusing on system-level verification for its Physical AI SoC. You will verify boot flows, security state transitions, and IO/memory subsystems across typical workloads.

The role requires leadership in verification projects and hands-on experience with CDC/RDC tools, low power flows, and emulation or FPGA prototyping to accelerate tape-out readiness.