Senior CPU Design Verification Engineer

Velaura; Santa Clara (CA); On-site; USD 200,000 - 350,000; Full time

Benefits offered by this job

Equity participation

Competitive base salary

Performance incentives

Job summary

Velaura in Santa Clara, California, is seeking a Design Verification Engineer to verify its next-generation Physical AI SoC focused on a custom CPU. You will collaborate with architects, RTL, software and system teams to ensure correctness, performance, reliability and safety across RTL blocks and complete hardware/software systems running real workloads.

You will own a functional verification domain from test plan through coverage closure, building portable environments using SystemVerilog,

Qualifications

• 8+ years verifying high performance CPUs or complex digital designs.
• Strong computer architecture and microarchitecture fundamentals.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience owning a block or unit of a design independently from test plan through coverage closure.
• Experience writing test plans, portable testbenches and transactors.
• Experience debugging complex issues across hardware and software boundaries.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.
• Ability to work effectively in a collaborative multidisciplinary engineering environment.

Responsibilities

• Own verification of custom CPU units including instruction fetch, decode, load store, and the instruction, data and last level caches.
• Work with CPU and SoC architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans.
• Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
• Develop instruction level stimulus and compare against a golden instruction set simulator.
• Verify memory ordering, coherence, exceptions and privilege behavior against the architecture specification.
• Verify latency, bandwidth and cache behavior against high performance targets under representative workloads.
• Execute regressions through design and environment bring up, and track progress using bug and coverage metrics.
• Support emulation, FPGA prototyping and pre silicon software bring up, and drive root cause analysis across hardware and software boundaries.

Skills

SystemVerilog

UVM

C/C++

Test plans

Assertions

Coverage-driven verification

Debugging HW/SW

Computer architecture

Microarchitecture fundamentals

Education

BS or higher in Computer Engineering, Electrical Engineering or Computer Science

Job description

Velaura in Santa Clara, California, is seeking a Design Verification Engineer to verify its next-generation Physical AI SoC focused on a custom CPU. You will collaborate with architects, RTL, software and system teams to ensure correctness, performance, reliability and safety across RTL blocks and complete hardware/software systems running real workloads.

You will own a functional verification domain from test plan through coverage closure, building portable environments using SystemVerilog,