Senior SoC Verification Engineer – System-Level

Velaura; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura is building next-generation Physical AI SoCs and seeks a senior Design Verification Engineer. You will verify and deliver complex hardware and software systems from RTL through tape-out, collaborating with architects, RTL and software engineers, and system teams.

The role focuses on system-level verification of boot, root of trust, clock/topology, low power, and IO/memory subsystems. Sign-off, coverage closure and tape-out readiness are key milestones.

Qualifications

• 10+ years in design verification with significant SoC level experience.
• Proven track record in sign-off and tape-out for complex SoCs.
• Expertise with SystemVerilog, UVM, C, and C++ for system-level verification.
• Experience managing CPU-based SoC verification flows on ARM or RISC-V.
• Knowledge of PCIe and LPDDR5/LPDDR6 memory interfaces.

Responsibilities

• Drive verification planning and execution for your assigned areas of the Velaura Physical AI SoC.
• Build and maintain SoC level simulation environments and flows for CPU based SoCs such as ARM or RISC-V.
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock and reset topology, power domains and low power behavior at system level.
• Verify IO and memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with the design teams.
• Verify system level latency, bandwidth and QoS under representative workloads.
• Support SoC sign off criteria, coverage closure and tape out readiness.

Skills

SystemVerilog

UVM

C

C++

SoC verification

Boot sequences

Root of trust

Power management

Emulation

Tools

Emulation

FPGA prototyping

CDC tools

RDC tools

UPF flows

Job description

Velaura is building next-generation Physical AI SoCs and seeks a senior Design Verification Engineer. You will verify and deliver complex hardware and software systems from RTL through tape-out, collaborating with architects, RTL and software engineers, and system teams.

The role focuses on system-level verification of boot, root of trust, clock/topology, low power, and IO/memory subsystems. Sign-off, coverage closure and tape-out readiness are key milestones.