AI-SoC Design Verification Engineer

Velaura; Austin (TX); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Equity compensation

Medical, dental, vision coverage

Paid time off

Flexible work arrangements

Professional development opportunities

Job summary

Velaura is seeking Design Verification Engineers to verify next-generation Physical AI SoC. You will create verification environments, collaborate across RTL, software, and system teams, and ensure correctness, performance, and reliability from RTL blocks to full HW/SW platforms.

We welcome engineers at all levels who enjoy tackling corner cases and complex problems, with opportunities to engage in emulation, FPGA prototyping, and pre-silicon software bring-up.

Qualifications

• Experience verifying complex digital systems.
• Strong analytical and problem-solving skills.
• Solid understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.

Responsibilities

• Develop and execute verification strategies for key portions of the Velaura SoC.
• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

SystemVerilog

UVM

C/C++

Assertions

Formal verification

Debugging complex systems

Tools

Formal verification tools

Emulation platforms

FPGA prototyping

Job description

Velaura is seeking Design Verification Engineers to verify next-generation Physical AI SoC. You will create verification environments, collaborate across RTL, software, and system teams, and ensure correctness, performance, and reliability from RTL blocks to full HW/SW platforms.

We welcome engineers at all levels who enjoy tackling corner cases and complex problems, with opportunities to engage in emulation, FPGA prototyping, and pre-silicon software bring-up.