SoC Design Verification Engineer

Socket.dev; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Velaura is seeking a senior Design Verification Engineer to verify a next-generation Physical AI SoC. You will lead system-level verification across boot, root of trust, clock/reset topology, low power, and IO/memory subsystems, coordinating with architects, RTL and firmware teams.

Responsibilities include building SoC verification environments for ARM/RISC-V based CPUs, verifying boot flows and security transitions, and ensuring tape-out readiness.

Qualifications

• 10+ years in design verification, with notable SoC level experience.
• Leading or participating in multiple SoC verification projects including sign off and tape out.
• Experience with SystemVerilog, UVM, C/C++ and coverage-driven verification at system level.
• Experience managing simulation flows on CPU-based SoCs such as ARM or RISC‑V.
• Knowledge of IO and memory IP like PCIe and LPDDR5/LPDDR6.
• Experience verifying boot sequences and root of trust.
• Experience with CDC/RDC tools for system-level verification.
• Experience with low power verification tools and UPF based flows.

Responsibilities

• Drive verification planning and execution for assigned areas of the SoC.
• Build and maintain SoC-level simulation environments and flows for CPU-based SoCs (ARM or RISC-V).
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock/reset topology, power domains and low power behavior at system level.
• Verify IO/memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with design teams.
• Verify system-level latency, bandwidth and QoS under representative workloads.
• Support SoC sign-off criteria, coverage closure and tape-out readiness.

Skills

SystemVerilog

UVM

C/C++

SoC verification

ARM/RISC-V

PCIe/ LPDDR

Boot/root of trust

CDC/RDC

Low power verification

Sign-off / Tape-out

Tools

CDC tools

RDC tools

Emulation

FPGA prototyping

Job description

Role Overview

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role focuses on system level verification. The scope spans boot and root of trust, clock and reset topology, low power behavior, and the IO and memory subsystems that carry real traffic. You will work in one or more of these areas, matched to your strengths and to program needs, and carry that work through sign off and into tape out.

Responsibilities

• Drive verification planning and execution for your assigned areas of the Velaura Physical AI SoC.
• Build and maintain SoC level simulation environments and flows for CPU based SoCs such as ARM or RISC-V.
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock and reset topology, power domains and low power behavior at system level.
• Verify IO and memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with the design teams.
• Verify system level latency, bandwidth and QoS under representative workloads.
• Support SoC sign off criteria, coverage closure and tape out readiness.

Required Qualifications

• 10 or more years in design verification, including significant SoC level experience.
• Experience leading or participating in multiple SoC verification projects, including sign off and tape out.
• Experience with SystemVerilog, UVM, C and C++ and coverage driven verification at system level.
• Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
• Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
• Experience verifying boot sequences and root of trust.
• Experience verifying clock and reset topology at system level, with hands on use of CDC and RDC tools.
• Experience with low power verification tools and UPF based flows.

Preferred Qualifications

• Depth in one or more areas such as security, memory subsystem, interconnect or power management.
• Experience with HW and SW co verification and pre silicon software bring up.
• Experience with emulation and FPGA prototyping at SoC level.
• Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.
• Experience verifying QoS, latency sensitive or real time systems.
• Experience with post silicon bring up, debug and root cause analysis.
• Familiarity with robotics, drones, autonomous vehicles or industrial automation systems.
• Experience using AI assisted verification workflows to improve productivity and coverage.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case-by-case basis.