SoC Design Verification Lead

Socket.dev; Santa Clara (CA); On-site; USD 210,000 - 270,000; Full time

Job summary

Velaura is seeking an experienced verification leader to drive the SoC verification strategy for the Velaura Physical AI SoC. You will lead a small team, stay hands-on, and work with architects, RTL, firmware, and system teams to ensure correct, reliable performance and safety from RTL blocks to full systems.

You will own the verification plan through sign-off, coordinating boot, security, clock/topology, low power, IO and memory subsystems, and driving coverage to tape-out readiness.

Qualifications

• 12+ years in design verification, with major SoC level exposure.
• Proven track at leading SoC verification across sign-off and tape-out.
• Experience building and leading verification teams.
• Proficient in SystemVerilog, UVM, C/C++, and coverage-driven verification.
• Experience with ARM or RISC-V CPU-based verification and SoC interconnects like PCIe.
• Strong cross-team communication and leadership.

Responsibilities

• Own SoC level verification strategy and plan through tape-out.
• Build and lead a team of verification engineers.
• Define verification architecture and environment; hands-on coding.
• Coordinate verification across boot, security, clocks, power, IO and memory.
• Define sign-off criteria and ensure coverage goals.
• Track progress, coverage, and risk to leadership.
• Collaborate with architecture, RTL, DFT, firmware, and software teams.
• Partner with CAD for simulation, emulation, and regression capacity.

Skills

SystemVerilog

UVM

C/C++

SoC verification

Leadership

ARM/RISC-V

PCIe/LPDDR

CDC/RDC/UPF

Boot/RT verification

Communication

Tools

Emulation

FPGA Prototyping

Simulation Tools

Job description

Role Overview

We are looking for an experienced verification leader to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role leads system level verification. You will own the SoC verification plan and carry it through sign off and into tape out, covering boot and root of trust, clock and reset topology, low power behavior, and the IO and memory subsystems. You will set technical direction for a small team while staying hands on in the environment yourself.

Responsibilities

• Own the SoC level verification strategy, plan and execution for the Velaura Physical AI SoC.
• Build and lead a team of SoC verification engineers, setting technical direction and reviewing their work.
• Define the SoC verification architecture and environment, and stay hands on in the code.
• Coordinate verification across boot and security, clock and reset, low power, and the IO and memory subsystems.
• Define sign off criteria and coverage goals, and drive closure through tape out.
• Track and report verification progress, coverage and risk to engineering leadership.
• Work with architecture, RTL, DFT, firmware and software teams on system level correctness and pre silicon bring up.
• Partner with CAD and infrastructure teams on simulation, emulation and regression capacity.

Required Qualifications

• 12 or more years in design verification, including significant SoC level experience.
• Experience leading SoC verification across multiple projects through sign off and tape out.
• Experience building and leading a team of verification engineers.
• Experience with SystemVerilog, UVM, C and C++ and coverage driven verification at system level.
• Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
• Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
• Experience verifying boot and root of trust, clock and reset topology, and low power behavior at system level, including CDC, RDC and UPF based flows.
• Excellent communication skills and the ability to influence engineering leaders across disciplines.

Preferred Qualifications

• Experience with HW and SW co verification and pre silicon software bring up.
• Experience with emulation and FPGA prototyping at SoC level.
• Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.
• Experience verifying QoS, latency sensitive or real time systems.
• Experience with post silicon bring up, debug and root cause analysis.
• Experience building a verification team at an early stage company.
• Familiarity with robotics, drones, autonomous vehicles or industrial automation systems.
• Experience using AI assisted verification workflows to improve productivity and coverage.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case-by-case basis.