Senior Mask & Interposer Design Engineer

NVIDIA Corporation; Santa Clara (CA); Remote; USD 168,000 - 259,000; Full time

Job summary

NVIDIA is seeking a Senior Mask Design Engineer to contribute to the detailed layout of silicon interposers for NVIDIA products. You will collaborate with PTL and I/O signal integrity teams to deliver tight-schedule packages using Cadence tools.

The role requires a BS in Electrical Engineering, 5+ years of mask/layout experience, deep CMOS layout knowledge, and Cadence Virtuoso expertise, plus scripting and verification tool familiarity.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• Minimum of 5+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• You are an authority with Cadence layout tools - particularly Virtuoso.
• Knowledge of Integrity auto-routing is a plus.
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Should have knowledge of DRC and LVS checking flows, ability to customize decks.
• Knowledge of APD package layout tool is a plus.
• Good understanding of packaging technology is useful.
• You can work optimally in a team, good interpersonal skills, passion and positive energy.

Responsibilities

• Collaborate cross functionally with PTL and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

Skills

Strong teamwork

Good interpersonal skills

Problem solving

Automation scripting experience

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Virtuoso

Integrity auto-routing

Calibre

ICV

Thunder

Perl

Python

Skill (Cadence)

APD package layout tool

Job description

NVIDIA is seeking a Senior Mask Design Engineer to contribute to the detailed layout of silicon interposers for NVIDIA products. You will collaborate with PTL and I/O signal integrity teams to deliver tight-schedule packages using Cadence tools.

The role requires a BS in Electrical Engineering, 5+ years of mask/layout experience, deep CMOS layout knowledge, and Cadence Virtuoso expertise, plus scripting and verification tool familiarity.