Senior Mask & Layout Engineer – Interposer Cadence

NVIDIA; Santa Clara (CA); Hybrid; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior Mask Design Engineer to design and develop intricate silicon interposer layouts, collaborating across design teams to meet aggressive schedules. You will drive feasibility studies, optimize layouts, and verify with established tools, leveraging Cadence Virtuoso and scripting to streamline processes.

The role requires 3+ years in mask/layout design, deep CMOS layout knowledge, and strong problem-solving abilities. Hybrid work and equity/benefits are offered.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• 3+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• Expertise with Cadence layout tools, especially Virtuoso.
• Knowledge of DRC/LVS flows and deck customization.
• Experience with verification tools (Calibre/ICV/Thunder).
• Proficiency in scripting (Perl/Python/Skill).
• Knowledge of APD packaging layout tool is a plus.

Responsibilities

• Collaborate cross-functionally with PTL and I/O engineers to deliver layouts on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct feasibility studies evaluating size, cost, and performance.
• Study floorplans and perform custom layout with netlist verification.
• Propose layout trade-offs to PTL for resolution and implementation.

Skills

Mask & Layout Design

Cadence Virtuoso

Submicron CMOS concepts

Scripting: Perl/Python/Skill

DRC/LVS/Deck customization

Integrity auto-routing

Verification tools: Calibre/ICV/Thunde

Education

B.S. Electrical Engineering

Tools

Calibre

ICV

Thunder

Virtuoso

Job description

NVIDIA seeks a Senior Mask Design Engineer to design and develop intricate silicon interposer layouts, collaborating across design teams to meet aggressive schedules. You will drive feasibility studies, optimize layouts, and verify with established tools, leveraging Cadence Virtuoso and scripting to streamline processes.

The role requires 3+ years in mask/layout design, deep CMOS layout knowledge, and strong problem-solving abilities. Hybrid work and equity/benefits are offered.