Senior Mask Design Engineer - Interposer Layout

NVIDIA Corporation; Santa Clara (CA); On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Mask Design Engineer to contribute to the layout of silicon interposers and collaborate with package teams to meet aggressive timelines.

You will perform physical layout using Cadence tools, evaluate design goals for size, cost and performance, and verify against rules and netlists. A BS in EE and 3+ years in mask/layout are required, with strong scripting and PD flows experience.

Qualifications

• BS E.E. or equivalent with 3+ years in mask and layout design.
• Strong understanding of submicron CMOS layouts.
• Experience with Cadence Virtuoso required.
• Knowledge of DRC and LVS flows; ability to customize decks.

Responsibilities

• Collaborate cross-functionally with PTL and I/O signal integrity engineers to deliver package solutions on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies evaluating size, cost, and system performance.
• Study layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to PTL for resolution and implementation.

Skills

Scripting

Teamwork

Problem-solving

Education

Bachelor's degree in Electrical Engineering

3+ years in Mask and Layout Design

Tools

Cadence Virtuoso

Calibre

ICV

Thunder

Integrity Auto-routing

APD packaging tool

DRC/LVS flows

Job description

NVIDIA Corporation is seeking a Senior Mask Design Engineer to contribute to the layout of silicon interposers and collaborate with package teams to meet aggressive timelines.

You will perform physical layout using Cadence tools, evaluate design goals for size, cost and performance, and verify against rules and netlists. A BS in EE and 3+ years in mask/layout are required, with strong scripting and PD flows experience.