Senior Mask Design Engineer: Silicon Interposer & Packaging

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Hybrid work

Job summary

NVIDIA Corporation is seeking a Senior Mask Design Engineer in Santa Clara, CA, to design and develop intricate silicon interposer layouts for NVIDIA products. You will collaborate with cross-functional teams to meet tight schedules and optimize performance and cost.

The role requires hands-on expertise in mask and layout design, Cadence Virtuoso, and experienced use of verification tools. A strong scripting capability (Perl/Python) and knowledge of DRC/LVS are essential, with APD packaging

Qualifications

• B.S. Electrical Engineering or equivalent experience.
• 3+ years of mask and layout design experience.
• Deep understanding of submicron CMOS layout concepts.
• Proficient with Cadence layout tools, especially Virtuoso.
• Experience with verification tools such as Calibre, ICV, Thunder.
• Proficiency in scripting languages such as Perl and Python.
• Knowledge of DRC and LVS checking flows and deck customization is a plus.
• Knowledge of APD package layout tools is a plus.
• Understanding packaging technology is useful.

Responsibilities

• Collaborate cross-functionally with PTL and engineers to deliver package solutions within tight schedules.
• Perform physical layout for silicon interposers using Cadence tools.
• Conduct design feasibility studies to evaluate package goals (size, cost, performance).
• Study layout floorplans and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

Skills

Mask design

Layout design

Cadence Virtuoso

Perl/Python

DRC/LVS debugging

Team collaboration

Education

B.S. Electrical Engineering or equivalent experience

Tools

Calibre

ICV

Thunder

APD package layout tool

APD package tooling

Perl

Python

Job description

NVIDIA Corporation is seeking a Senior Mask Design Engineer in Santa Clara, CA, to design and develop intricate silicon interposer layouts for NVIDIA products. You will collaborate with cross-functional teams to meet tight schedules and optimize performance and cost.

The role requires hands-on expertise in mask and layout design, Cadence Virtuoso, and experienced use of verification tools. A strong scripting capability (Perl/Python) and knowledge of DRC/LVS are essential, with APD packaging