Senior Mask Design Engineer: Interposer Layout & Cadence

NVIDIA; North Carolina; On-site; USD 168,000 - 259,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Mask Design Engineer in North Carolina to drive advanced silicon interposer layout and related package design efforts. You will collaborate with PTL and diverse design teams to achieve high-performance, cost-efficient layouts on aggressive schedules.

Responsibilities include physical layout, feasibility studies, and layout verification using Cadence Virtuoso and industry tools. A strong background in submicron CMOS and scripting is essential for success.

Qualifications

• B.S. in Electrical Engineering or equivalent.
• 5+ years of proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• Proficiency with Cadence layout tools, especially Virtuoso.
• Experience with verification tools such as Calibre, ICV, Thunder.
• Scripting skills in Perl, Python, or SKILL.
• Knowledge of DRC/LVS flows and deck customization.
• Knowledge of APD package layout tool is a plus.

Responsibilities

• Collaborate cross-functionally with package tech lead and engineers to deliver solutions within tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate goals for size, cost, and performance.
• Study layout floorplans and perform custom layout and verification against rules and netlists.
• Propose layout trade-offs to the PTL for resolution and implementation.

Skills

B.S. in Electrical Engineering

Mask & Layout Design

Cadence Virtuoso

Scripting: Perl/Python/Skill

DRC/LVS flows

Calibre/ICV/Thunder

Integrity auto-routing

Education

B.S. Electrical Engineering

Tools

Cadence Virtuoso

Calibre

ICV/Thunder

Job description

NVIDIA is seeking a Senior Mask Design Engineer in North Carolina to drive advanced silicon interposer layout and related package design efforts. You will collaborate with PTL and diverse design teams to achieve high-performance, cost-efficient layouts on aggressive schedules.

Responsibilities include physical layout, feasibility studies, and layout verification using Cadence Virtuoso and industry tools. A strong background in submicron CMOS and scripting is essential for success.