Senior Mask Design Engineer – Silicon Interposer Layout

NVIDIA; Oregon (WI); On-site; USD 136,000 - 259,000; Full time

Job summary

NVIDIA is seeking a Senior Mask Design Engineer to advance deep submicron layout for silicon interposers. You will collaborate with PTL and I/O teams, performing physical layout with Cadence Virtuoso and evaluating design tradeoffs under tight schedules.

The role requires a BS in Electrical Engineering and 5+ years in mask and layout design, with experience Calibre/ICV, DRC/LVS flows, and scripting in Perl/Python. Base salary ranges and equity/benefits accompany a competitive package.

Qualifications

• B.S. Electrical Engineering or equivalent experience.
• 5+ years in Mask and Layout Design.
• Deep understanding of submicron CMOS layouts.
• Proficient with Cadence tools, especially Virtuoso.
• Knowledge of DRC/LVS flows and deck customization.

Responsibilities

• Collaborate with PTL and I/O engineers to meet tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies for size, cost and performance.
• Study floorplan and perform custom layout with verification against rules and nets.
• Propose trade-offs to PTL for resolution and implementation.

Skills

Layout concepts

Submicron CMOS

Scripting languages

Education

B.S. Electrical Engineering

Tools

Cadence Virtuoso

Calibre

ICV

Thunder

Job description

NVIDIA is seeking a Senior Mask Design Engineer to advance deep submicron layout for silicon interposers. You will collaborate with PTL and I/O teams, performing physical layout with Cadence Virtuoso and evaluating design tradeoffs under tight schedules.

The role requires a BS in Electrical Engineering and 5+ years in mask and layout design, with experience Calibre/ICV, DRC/LVS flows, and scripting in Perl/Python. Base salary ranges and equity/benefits accompany a competitive package.