Senior Mask Design Engineer – Silicon Interposers

NVIDIA; Arizona; On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA invites a Senior Mask Design Engineer to shape silicon interposers and collaborate with the Package Technical Lead and cross-functional design teams to meet tight schedules and resolve cost and manufacturing challenges.

The role centers on physical layout using Cadence tools, conducting feasibility studies, studying floorplans, and verifying layouts against netlists and design rules, with opportunities to optimize trade-offs.

Qualifications

• B.S. Electrical Engineering or equivalent experience.
• 3+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• Cadence tools expertise, especially Virtuoso.
• Experience with verification tools such as Calibre, ICV, Thunder.
• Proficient in Perl, Python, and Skill scripting.
• Knowledge of DRC/LVS flows and deck customization.
• APD package layout tool knowledge is a plus.
• Good packaging technology understanding.
• Teamwork and positive interpersonal skills.

Responsibilities

• Collaborate cross functionally with PTL and I/O signal integrity/tech engineers to deliver solutions on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies for size, cost, and performance goals.
• Study layout floorplans and perform custom layout and verification against netlists.
• Propose layout trade-offs to PTL for resolution and implementation.

Skills

Scripting languages

Teamwork

Interpersonal skills

Problem solving

Communication

Education

B.S. Electrical Engineering

Tools

Cadence Virtuoso

Calibre

ICV

Thunder

APD layout tool

Job description

NVIDIA invites a Senior Mask Design Engineer to shape silicon interposers and collaborate with the Package Technical Lead and cross-functional design teams to meet tight schedules and resolve cost and manufacturing challenges.

The role centers on physical layout using Cadence tools, conducting feasibility studies, studying floorplans, and verifying layouts against netlists and design rules, with opportunities to optimize trade-offs.