Remote Senior DFT Engineer – SoC Test Architect

Encore Semi, Inc.; Boston (MA); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10

Medical benefits 80%

Dental & Vision 50%

Voluntary benefits

EAP

401k

Life/AD&D

LT Disability

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs, collaborating with design and verification teams from RTL to silicon bring-up. This full-time remote position in the USA offers salary plus comprehensive benefits.

Requires 8+ years in ASIC DFT, IJTAG with IEEE 1687, experience with Mentor Tessent, and strong Verilog/SystemVerilog and scripting skills (Tcl/Python/Perl). BS/MS in EE or CE is required.

Qualifications

• 8+ years of proven industry experience in ASIC DFT engineering.
• IEEE 1687 IJTAG architecture experience (ICL and PDL formats).
• Proficiency with Mentor Tessent tool suite (Siemens).
• Simulation/verification/debug using Xcelium, VCS or QuestaSim.
• Fluency in Verilog/SystemVerilog; strong scripting (Tcl, Python, Perl).
• BS or MS in Electrical Engineering, Computer Engineering, or related field.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

8+ years ASIC DFT experience

IJTAG IEEE 1687

Tessent tools

Verilog/SystemVerilog

Tcl/Python/Perl scripting

Education

BS/MS in Electrical/Computer Engineering

Tools

Mentor Tessent

Xcelium

VCS

QuestaSim

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs, collaborating with design and verification teams from RTL to silicon bring-up. This full-time remote position in the USA offers salary plus comprehensive benefits.

Requires 8+ years in ASIC DFT, IJTAG with IEEE 1687, experience with Mentor Tessent, and strong Verilog/SystemVerilog and scripting skills (Tcl/Python/Perl). BS/MS in EE or CE is required.