Senior DFT Engineer - Remote SoC Test Architect

Encore Semi Llc; Austin (TX); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10

Medical benefits 80%

Dental & Vision 50%

Life Insurance & Disability

Tuition reimbursement

401k Traditional & Roth

EAP

Job summary

Encore Semi, Inc. seeks a Senior DFT Engineer to lead test architecture for complex SoCs, working from RTL to silicon bring-up. This 100% remote role supports collaboration with design and verification teams across the United States.

The ideal candidate has 8+ years in ASIC DFT, IJTAG (IEEE 1687) with ICL/PDL, and strong experience in Tessent, Xcelium, VCS, or QuestaSim. BS/MS in EE/CE is required.

Qualifications

• 8+ years of proven industry experience in ASIC DFT engineering.
• IEEE 1687 IJTAG architecture experience with ICL and PDL formats.
• Mentor Tessent tool suite proficiency.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

Verilog/SystemVerilog

Tcl scripting

Python scripting

Perl scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

Tessent (Mentor Graphics)

Xcelium

VCS

QuestaSim

Job description

Encore Semi, Inc. seeks a Senior DFT Engineer to lead test architecture for complex SoCs, working from RTL to silicon bring-up. This 100% remote role supports collaboration with design and verification teams across the United States.

The ideal candidate has 8+ years in ASIC DFT, IJTAG (IEEE 1687) with ICL/PDL, and strong experience in Tessent, Xcelium, VCS, or QuestaSim. BS/MS in EE/CE is required.