Remote Senior DFT Engineer - ASIC/SoC Test Architect

Encore Semi, Inc.; San Diego (CA); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

15 days PTO per year

10 paid holidays per year

Medical benefits: 80% premiums

Dental & Vision: 50% premiums

Life Insurance & Disability

401k - Traditional & Roth

EAP

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs in a fully remote role in the USA. You will collaborate with design and verification teams from RTL through silicon bring-up to ensure high test coverage.

The position requires 8+ years in ASIC DFT, strong IJTAG expertise, and proficiency with Tessent and major simulators. Competitive salary and comprehensive benefits are offered.

Qualifications

• 8+ years of ASIC DFT engineering experience.
• Hands-on IJTAG architecture with ICL and PDL formats.
• Deep proficiency with Tessent tool suite.
• Strong verification, debug, and simulation skills.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan).
• Develop IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run timing-annotated gate-level simulations and debugging.

Skills

Verilog

SystemVerilog

Scripting (Python/Tcl/Perl)

Education

BS EE or CE

MS in Electrical Engineering

Tools

Tessent (Mentor)

IJTAG (IEEE 1687)

Xcelium / VCS / QuestaSim

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs in a fully remote role in the USA. You will collaborate with design and verification teams from RTL through silicon bring-up to ensure high test coverage.

The position requires 8+ years in ASIC DFT, strong IJTAG expertise, and proficiency with Tessent and major simulators. Competitive salary and comprehensive benefits are offered.