Senior DFT Engineer - Remote SoC Test Architecture

Encore Semi Llc; San Diego (CA); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days/year

Holidays 10 days/year

Medical benefits (80% premiums) for E+

Dental & Vision (50% premiums)

Life Insurance & Disability

401k (Traditional & Roth)

Tuition reimbursement

EAP

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs, working remotely from anywhere in the USA. You will partner with design and verification teams to drive DFT from RTL through silicon bring-up, ensuring high fault coverage and robust test coverage.

The role requires 8+ years in ASIC DFT, strong Verilog/SystemVerilog and scripting skills, and expertise with IJTAG (IEEE 1687) and Tessent tools. A BS or MS in EE is required.

Qualifications

• 8+ years of ASIC DFT engineering experience.
• Strong expertise with IEEE 1687 (IJTAG) architecture and ICL/PDL formats.
• Proficient in Verilog/SystemVerilog and scripting languages.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-gen ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

IJTAG

Verilog/SystemVerilog

Scripting: Tcl/Python/Perl

DFT/ATPG concepts

IJTAG architectures (IEEE 1687)

Xcelium/VCS/QuestaSim

Tessent (Mentor Graphics)

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Mentor Tessent

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs, working remotely from anywhere in the USA. You will partner with design and verification teams to drive DFT from RTL through silicon bring-up, ensuring high fault coverage and robust test coverage.

The role requires 8+ years in ASIC DFT, strong Verilog/SystemVerilog and scripting skills, and expertise with IJTAG (IEEE 1687) and Tessent tools. A BS or MS in EE is required.