Senior DFT Engineer — Remote SoC Test Architect

Encore Semi Llc; Irvine (CA); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10 days

Medical benefits 80% premiums

Dental/ Vision 50% premiums

Life Insurance

Tuition reimbursement

401k (Traditional & Roth)

EAP

Disability

FSA/HAS

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs.

This role supports 100% remote work from anywhere in the USA, collaborating with design and verification teams to ensure comprehensive DFT coverage from RTL to silicon bring-up. The ideal candidate will have 8+ years of ASIC DFT experience, deep IJTAG expertise (ICL/PDL), proficiency with Tessent, and strong Verilog/SystemVerilog coding plus Tcl/Python/Perl scripting.

Qualifications

• 8+ years in ASIC DFT engineering.
• IEEE 1687 IJTAG architecture experience (ICL and PDL).
• Proficiency with Mentor Tessent tool suite.
• Strong Verilog/SystemVerilog skills; scripting in Tcl/Python/Perl.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

ASIC DFT

IJTAG

Verilog/SystemVerilog

Scripting (Tcl/Python/Perl)

Education

BS or MS in Electrical/Computer Engineering

Tools

Tessent

Xcelium

VCS

QuestaSim

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs.

This role supports 100% remote work from anywhere in the USA, collaborating with design and verification teams to ensure comprehensive DFT coverage from RTL to silicon bring-up. The ideal candidate will have 8+ years of ASIC DFT experience, deep IJTAG expertise (ICL/PDL), proficiency with Tessent, and strong Verilog/SystemVerilog coding plus Tcl/Python/Perl scripting.