Senior DFT Architect - Remote SoC/ASIC Testing

Encore Semi, Inc.; Baltimore (MD); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days/year

10 holidays/year

Medical benefits (80% premiums)

Dental & Vision (50% premiums)

Voluntary benefits: Life Insurance, FS

Employee Assistance Program

401k - Traditional & Roth

Life/AD&D and Long-Term Disability

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture from RTL to silicon bring-up in a fully remote role across the USA. The candidate will collaborate with design and verification teams to ensure top-notch test coverage and robust DFT implementations.

The role requires 8+ years of ASIC DFT experience, strong IJTAG expertise, and direct hands-on use of Tessent, Xcelium/VCS/QuestaSim, and Verilog/SystemVerilog. A BS/MS in EE or CE is required.

Qualifications

• 8+ years of proven ASIC DFT engineering experience.
• Hands-on with IEEE 1687 IJTAG architecture and PDL/ICL formats.
• Deep proficiency with Mentor Tessent tool suite.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan).
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run and debug gate-level simulations (zero-delay and timing-annotated).

Skills

ASIC DFT

IJTAG (IEEE 1687)

Verilog/SystemVerilog

Scripting (Python/Tcl/Perl)

Debug & fault coverage

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Mentor Tessent

Xcelium

VCS

QuestaSim

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture from RTL to silicon bring-up in a fully remote role across the USA. The candidate will collaborate with design and verification teams to ensure top-notch test coverage and robust DFT implementations.

The role requires 8+ years of ASIC DFT experience, strong IJTAG expertise, and direct hands-on use of Tessent, Xcelium/VCS/QuestaSim, and Verilog/SystemVerilog. A BS/MS in EE or CE is required.