Senior DFT Architect – Remote ASIC/SoC Testing

Encore Semi, Inc.; Rochester (MN); A distancia; USD 135.000 - 150.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

15 PTO days

10 holidays per year

Comprehensive medical benefits (80% of

Dental & Vision 50% premiums

Life Insurance

401k - traditional & Roth

Tuition reimbursement

Employee Assistance Program (EAP)

Descripción de la vacante

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for next-generation SoCs in a fully remote role. You will collaborate with design and verification teams to define DFT requirements from RTL to silicon bring-up, ensuring high fault coverage and robust test delivery.

The position requires 8+ years in ASIC DFT, strong IJTAG (IEEE 1687) experience, proficiency with Mentor Tessent, and solid Verilog/SystemVerilog plus scripting (Tcl/Python/Perl). A BS/MS in EE is expected.

Formación

• 8+ years of ASIC DFT engineering experience.
• IEEE 1687 IJTAG architecture expertise with ICL and PDL formats.
• Deep proficiency with Mentor Tessent tool suite.
• Solid simulation/verification/debug skills (Xcelium, VCS, QuestaSim).
• Fluency in Verilog/SystemVerilog and scripting (Tcl/Python/Perl).
• BS or MS in Electrical or Computer Engineering.

Responsabilidades

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Conocimientos

ASIC DFT

IJTAG 1687

Tessent tools

Verilog/SystemVerilog

Tcl/Python/Perl

ATPG/Fault coverage

Educación

BS or MS in Electrical/Computer Engineering

Herramientas

Xcelium/Questa/VCS

Mentor Tessent

Descripción del empleo

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for next-generation SoCs in a fully remote role. You will collaborate with design and verification teams to define DFT requirements from RTL to silicon bring-up, ensuring high fault coverage and robust test delivery.

The position requires 8+ years in ASIC DFT, strong IJTAG (IEEE 1687) experience, proficiency with Mentor Tessent, and solid Verilog/SystemVerilog plus scripting (Tcl/Python/Perl). A BS/MS in EE is expected.