Senior Staff Engineer, DFT

AMBIQ MICRO SINGAPORE PRIVATE LTD.; Singapore; On-site; SGD 100,000 - 150,000; Full time

Job summary

A leader in ultra-low-power semiconductor solutions is seeking an experienced engineer specializing in Design for Test (DFT) implementation for ultra-low power SoCs. The role involves responsibilities from scan insertion to developing DFT architectures and improving test coverage. Candidates must have at least 10 years of experience, a BS/MS in ECE/EE, and expertise in various DFT techniques. This position offers a dynamic environment focused on innovation and technology advancement in Singapore.

Qualifications

• 10+ years of experience in DFT implementation.
• Extensive knowledge of DFT structures and low-power DFT.
• Strong experience in test time and coverage analysis.

Responsibilities

• Responsible for scan insertion and boundary scan for ultra-low power SoC.
• Develop low-power DFT architecture.
• Generate test vectors and improve test coverage.

Skills

DFT implementation

Low-Power DFT

Scan ATPG

Tcl scripting

Communication skills

Test coverage analysis

Education

BS/MS in ECE/EE

Tools

Standard EDA tools

RTL

GLS (gate level simulation)

Job description

Company Overview

Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub- and near-threshold technologies. With increased power requirements of artificial intelligence (AI) computing, our customers increasingly rely on our solutions to deliver AI to edge environments. Our hardware and software innovations fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs without expensive process geometry scaling. We started in 2010 addressing the needs of battery-powered devices at the edge, where power consumption challenges were most profound. As of the beginning of 2025, we’ve shipped more than 270 million units worldwide.

Our innovative and fast-moving teams of design, research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value relentless technology innovation, a deep commitment to customer success, collaborative problem-solving, and an enthusiastic pursuit of energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, meaningful, and challenging projects that will create a lasting impact and shape the future of technology. Join us on our quest for 100 billion devices. The edge intelligence revolution starts here.

Specific Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors, analyse, and improve coverage, test time and test cost.
• Perform pre/post-layout scan and MBIST simulations.
• Work with designers on STA, physical, power and logical issues related to DFT.
• Work with test engineers to bring up test vectors on silicon.

Requirements

Specific Experience

• BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
• Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
• Experience in creating and implementing hierarchical DFT architecture in complex SoC.
• Experience in Low-Power DFT and MBIST.
• Experience in test time and test coverage analysis for scan and MBIST patterns.
• Experience in working with test engineering team to bring up production test program.
• Extensive knowledge of timing concepts and constraint development.
• Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
• Experience in RTL is required.
• Experience in scripting like Tcl is preferred.
• Experience with GLS (gate level simulation) is preferred.
• Motivated, self-driven engineer with attention to detail.
• Strong verbal and written English communication skills.