Principal Design Engineer — RTL/Timing, Synthesis & Power

Ambition Singapore; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A recruitment agency in Singapore is seeking an engineer with expertise in using Synopsys/Cadence tools for design synthesis and Static Timing Analysis. The ideal candidate will hold a degree in Electrical/Electronic Engineering and possess strong TCL scripting skills. Responsibilities include creating timing constraints, performing STA, and collaborating with design teams. Candidates should be team players with good communication skills. This role offers the chance to work on challenging designs in a dynamic environment.

Qualifications

• Degree in Electrical/Electronic Engineering (Bachelor's or Master's).
• Hands-on experience with Synopsys or Cadence tool suites.
• Strong TCL scripting skills; Python is a plus.

Responsibilities

• Use Synopsys/Cadence tools to synthesize designs from RTL to netlist.
• Create timing constraints for functional and test modes, working closely with design and DFT teams.
• Perform Static Timing Analysis (STA) and achieve timing closure.
• Run logic equivalence checks to ensure correctness.

Skills

Hands-on experience with Synopsys or Cadence tool suites

Strong TCL scripting skills

Good communication skills

Education

Degree in Electrical/Electronic Engineering (Bachelor's or Master's)

Job description

A recruitment agency in Singapore is seeking an engineer with expertise in using Synopsys/Cadence tools for design synthesis and Static Timing Analysis. The ideal candidate will hold a degree in Electrical/Electronic Engineering and possess strong TCL scripting skills. Responsibilities include creating timing constraints, performing STA, and collaborating with design teams. Candidates should be team players with good communication skills. This role offers the chance to work on challenging designs in a dynamic environment.