Lead Physical Design Engineer: Timing Closure & Power

AMBITION GROUP SINGAPORE PTE. LTD.; Singapore; On-site; SGD 60,000 - 85,000; Full time

Job summary

A leading engineering firm in Singapore is seeking candidates for a role involving the use of Synopsys and Cadence tools to synthesize designs from RTL to netlist. The ideal candidate will hold a degree in Electrical or Electronic Engineering and possess hands-on experience with these tools. Responsibilities include creating timing constraints and performing Static Timing Analysis. Strong TCL scripting skills are required, and the ability to communicate effectively is essential.

Qualifications

• Hands-on experience with Synopsys or Cadence tool suites.
• Strong TCL scripting skills, Python is a plus.
• Ability to work independently and meet deadlines.

Responsibilities

• Use Synopsys/Cadence tools to synthesize designs from RTL to netlist.
• Create timing constraints for functional and test modes.
• Perform Static Timing Analysis (STA) and achieve timing closure.

Skills

Hands-on experience with Synopsys or Cadence tool suites

Strong TCL scripting skills

Good communication skills (written and verbal)

Education

Degree in Electrical/Electronic Engineering (bachelor’s or Master’s)

Job description

A leading engineering firm in Singapore is seeking candidates for a role involving the use of Synopsys and Cadence tools to synthesize designs from RTL to netlist. The ideal candidate will hold a degree in Electrical or Electronic Engineering and possess hands-on experience with these tools. Responsibilities include creating timing constraints and performing Static Timing Analysis. Strong TCL scripting skills are required, and the ability to communicate effectively is essential.