Foundation IP Design Engineer

Broadcom; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology firm in Singapore is seeking energetic and passionate memory design engineers to join their elite memory team. Responsibilities include analyzing memory architectures, designing memory blocks, and simulating circuit designs. Ideal candidates should possess knowledge in memory compilers, circuit behavior, and demonstrate good communication skills. A minimum of a BS in Electrical Engineering and 2 years of experience is required for this exciting opportunity.

Qualifications

• Requires 2+ years of related experience.

Responsibilities

• Analyze different memory architectures and highlight the tradeoffs.
• Design and build memory or circuit blocks at the gate or transistor level.
• Simulate and analyze circuit design using transistor level simulators.
• Extract the layout and perform post‑layout simulations.
• Floorplan physical implementation and leafcell layout integration.
• Integrate characterization flow to extract timing and power information.
• Develop scripts to automate characterization flow and verification.
• Document design specifications and timing diagrams.

Skills

Knowledge in memory compilers or custom digital circuits

Understanding of transistor level circuit behavior

Good communication and interpersonal skills

Proficient in running simulators

Motivated and self‑driven

Education

BS in Electrical Engineering

Job description

Job Description

We are looking for energetic and passionate memory design engineers to join our Central Engineering Group and be part of an elite memory team responsible for the development of memory compilers and custom macros of all types on the bleeding edge of process technology.

Available Job Responsibilities

• Analyze different memory architectures and highlight the tradeoffs
• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post‑layout simulations and verification
• Floorplan physical implementation and leafcell layout integration to build the physical macro
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Specify silicon test plan and correlate silicon to simulation data
• Help debug silicon issues

Skillset Required

• Knowledge in development of memory compilers or custom digital circuits of all types; SRAMs, Register‑files, Multi‑ports, ROM, etc…
• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity, EM/IR, and reliability analysis
• Understanding of memory behavioral and physical models
• Understanding of DFT schemes and chip level integration
• Familiarity with test setups, silicon testing and debug is a plus
• Proficient in running simulators, writing automation scripts, and are tools savvy
• Good communication, interpersonal, and leadership skills
• Motivated, self‑driven and good at multi‑tasking

Qualifications

Requires a BS in Electrical Engineering and 2+ years of related experience