Design Engineer- PNR/STA

Broadcom; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking a Design Engineer specialized in Place and Route and Static Timing Analysis (STA). This role involves automating flow development for digital/mixed signal blocks and working with cross-functional teams to resolve timing constraints. The ideal candidate will have a strong background in CAD tools like ICC2 and Innovus, requiring at least 4 years of experience in the relevant domain. Join a dynamic team to contribute to cutting-edge technology projects.

Qualifications

• Minimum 4 years of experience for B.S. degree candidates.
• Minimum 2 years of experience for M.S. degree candidates.

Responsibilities

• Develop automation flow for complex digital/mixed signal blocks.
• Define Floor Plan/placement/routing/Timing constraints in ICC.
• Interact with cross-functional teams to resolve timing violations.
• Automate constraints to achieve predictable timing closure.
• Perform architectural feasibility analysis for PNR.

Skills

Hands-on experience with synthesis

Experience with ICC2, Fusion compiler

In-depth knowledge of power floor-plan

Familiarity with ECO implementation

Strong automation and scripting skills

Education

B.S. degree in relevant field

M.S. degree in relevant field

Tools

ICC2

PrimeTime

Innovus

TCL

Perl

Job description

Design Engineer: Place and Route (PNR), STA (Static Timing Analysis)

Broadcom Central Engineering Group is looking for energetic and passionate Place and Route/STA Engineer. The successful candidate will be responsible to work in one or more domains of Place and Route, STA development for complex Digital IP subsystems, semi‑custom macros across all types of bleeding edge process technologies.

Job Responsibilities

• Netlist to GDS2 automation flow development for complex digital/mixed signal blocks using PNR tools like ICC2 or Innovus in advanced technology nodes.
• Define the Floor Plan/placement/routing/Timing constraints in ICC for complex blocks including BIST to achieve correct by‑construct DRC/LVS and timing closure.
• Interact with the cross‑functional team (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS.
• Constraints automation to achieve predictable timing closure through automation with minimal ECOs.
• Perform PNR architectural feasibilities with multiple power islands with optimum utilization, EM, IR.
• Develop fully automated PNR, STA development flow to close timing to meet broader frequency requirements.

Skill Sets

• Hands‑on experience with synthesis, ICC2, Fusion compiler, Innovus, PrimeTime tools.
• Hands‑on experience in defining ICC2/synthesis constraints that meet timing closure needs.
• In‑depth knowledge of signal and power floor‑plan with minimal EM/IR violations.
• In‑depth expertise with all ICC2/STA options to handle de‑ratings, options to reduce crosstalk.
• Familiarity with ECO implementation, tools like Tweaker.
• Hands‑on expertise with TCL/Perl to automate the end‑to‑end PNR/STA flow.
• Experience handling a complex netlist with multiple frequency domains and ICC timing closure.
• Hands‑on experience analyzing and correlating STA vs. ICC timing reports.
• Complete exposure to Synopsys timing‑closure tools; Star‑RC, PrimeTime, PTSI. Exposure to Cadence timing‑closure flow is a big plus.
• Strong automation and scripting skills using Perl/Python to analyze timing/noise reports and drive swift timing closure.

Additional Traits

• Strong team player with ability to work across multiple geographies.
• Strong technical and behavioral competency with a can‑do attitude in driving complex projects.

Qualification

• B.S. degree with minimum 4+ years’ experience in the relevant domain.
• M.S. degree with minimum 2+ years’ experience in the relevant domain.