Senior FPGA Architect — PCIe Prototyping & Verification

Synopsys, Inc.; Porto; Hybrid; EUR 60,000 - 90,000; Full time

Job summary

Synopsys Porto is seeking an experienced FPGA design engineer to drive high-performance PCIe solutions from architecture through timing closure. You will collaborate across hardware, software, and verification teams to deliver reliable FPGA prototypes and meet stringent industry standards.

The role focuses on RTL design in Verilog, multi-clock domains, and PCIe protocol debugging within a dynamic engineering team in Porto.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent hands-on experience.
• 8+ years of FPGA design and development experience shipping working designs.
• Deep proficiency in Verilog RTL design, including state machines, pipelines, and multi-clock domains.
• Strong command of Vivado or similar FPGA toolchains covering synthesis, implementation, and timing closure.
• Solid understanding of digital design fundamentals: clock domain crossings, metastability, timing constraints, and static timing analysis.
• Experience with PCIe or Ethernet, including protocol-level debugging.
• Scripting in Python or Tcl for automation is a plus.

Responsibilities

• Prototype and optimize high-performance PCIe-based designs on FPGA platforms using Vivado.
• Simulate and verify PCIe-based prototype designs using industry-standard verification methodologies such as UVM, ensuring correct functionality prior to FPGA implementation.
• Perform timing analysis and optimization across multiple clock domains, resolving setup and hold violations.
• Collaborate with hardware, software, and verification teams to define requirements and evaluate design tradeoffs.
• Develop and execute test plans to validate functionality, performance, and reliability of FPGA prototypes.
• Participate in PCI-SIG Compliance Workshops and perform official compliance testing.
• Debug and resolve hardware, protocol, and system-level issues identified during PCIe testing.

Skills

FPGA design

Verilog RTL

Multi-clock domains

Timing analysis

Debugging

Documentation

Team collaboration

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Vivado

Job description

Synopsys Porto is seeking an experienced FPGA design engineer to drive high-performance PCIe solutions from architecture through timing closure. You will collaborate across hardware, software, and verification teams to deliver reliable FPGA prototypes and meet stringent industry standards.

The role focuses on RTL design in Verilog, multi-clock domains, and PCIe protocol debugging within a dynamic engineering team in Porto.