Senior ASIC Digital Verification Engineer (HBM/PCIe)

Synopsys Inc; Moreira; Presencial; EUR 55 000 - 75 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health benefits

Wellness programs

Financial benefits

Resumo da oferta

Synopsys Porto is seeking an experienced ASIC Digital Verification Engineer to join our team. You will develop verification plans for HBM-based ASIC designs, build and maintain test benches, and collaborate with design and architecture teams to ensure specifications are met.

You will apply UVM and SystemVerilog in simulation environments, debug issues, and document verification results to drive continuous improvement.

Qualificações

• Extensive experience in ASIC digital verification, particularly with HBM protocols.
• Proficiency in industry-standard verification tools such as UVM and SystemVerilog.
• Strong understanding of digital design principles and methodologies.
• Experience with creating and maintaining complex test benches and verification environments.

Responsabilidades

• Develop verification plans and strategies for HBM-based ASIC designs.
• Creating and maintaining test benches, test cases, and verification environments using industry-standard tools and methodologies.
• Collaborating with design and architecture teams to understand design specifications and requirements.
• Performing functional and performance verification to ensure the design meets all specifications and requirements.
• Debugging and resolving issues identified during verification and working closely with design teams to implement fixes.
• Documenting verification processes, results, and providing feedback for continuous improvement.

Conhecimentos

ASIC digital verification

HBM protocols

Ferramentas

UVM

SystemVerilog

Descrição da oferta de emprego

Synopsys Porto is seeking an experienced ASIC Digital Verification Engineer to join our team. You will develop verification plans for HBM-based ASIC designs, build and maintain test benches, and collaborate with design and architecture teams to ensure specifications are met.

You will apply UVM and SystemVerilog in simulation environments, debug issues, and document verification results to drive continuous improvement.