Secure RTL Design Engineer for Trustworthy IP

Synopsys, Inc.; Porto; Híbrido; EUR 60 000 - 90 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health benefits

Financial benefits

Salary range discussed

Resumo da oferta

Synopsys, Inc. in Porto is seeking a highly skilled RTL design engineer for Security IP cores. You will translate security requirements into synthesizable hardware and build robust test environments using SystemVerilog and UVM to cover corner cases and attack scenarios.

You will verify IP cores and subsystems with modern verification approaches, including UVM testbenches and formal methods, while collaborating with security engineers to assess correctness and performance across threat models.

Qualificações

• MSc or PhD in Electrical Engineering, Computer Science, or a related technical discipline.
• Proficient in writing synthesizable Verilog/SystemVerilog.
• Experience with ASIC verification using SystemVerilog/UVM in real projects.
• Knowledge of hardware security concepts is a plus.

Responsabilidades

• Design and implement RTL in Verilog and SystemVerilog for Security IP cores, translating security requirements into synthesizable hardware.
• Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM, ensuring coverage of corner cases and attack scenarios.
• Verify IP cores and subsystems using modern verification techniques including UVM testbenches and formal verification tools.
• Collaborate with hardware and software security engineers to analyze functional correctness and performance of embedded IP solutions across threat models.
• Contribute to detailed design specifications, verification plans, and documentation that support global development and customer integration.
• Work within an international team across time zones, coordinating design reviews, debugging sessions, and milestone deliveries.

Conhecimentos

RTL design

Verilog/SystemVerilog

UVM

ASIC verification

Security IP

Debugging

Formação académica

MSc/PhD in EE/CS

Descrição da oferta de emprego

Synopsys, Inc. in Porto is seeking a highly skilled RTL design engineer for Security IP cores. You will translate security requirements into synthesizable hardware and build robust test environments using SystemVerilog and UVM to cover corner cases and attack scenarios.

You will verify IP cores and subsystems with modern verification approaches, including UVM testbenches and formal methods, while collaborating with security engineers to assess correctness and performance across threat models.