Senior RTL Engineer: SoC Design & Tape-out Lead

Capgemini Engineering; Porto; Vor Ort; EUR 65.000 - 90.000; Vollzeit

Benefits dieser Stelle

Health and life insurance

Referral program with bonuses fortal…

Great office locations

Zusammenfassung

Capgemini Engineering is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out for high-performance, power-efficient SoCs. You will define microarchitectures, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across verification, synthesis, and physical design teams to ensure timing, power and area targets.

The role requires 6+ years in RTL/ASIC/VLSI, strong HDL skills, and experience with Lint/CDC/Low Power methodologies, STA, and CPU architectures.

Qualifikationen

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in RTL, ASIC, SoC, or VLSI design.
• Strong knowledge of Verilog, SystemVerilog, and/or VHDL.
• Proven experience in microarchitecture definition and complex digital design development.
• Solid understanding of SoC design methodologies and integration.
• Hands-on experience with Lint, CDC, and Low Power design methodologies.
• Good knowledge of synthesis flows and Static Timing Analysis (STA).
• Familiarity with CPU architectures and instruction sets such as ARM, RISC-V, or x86.
• Experience with scripting and programming languages such as Python, Perl, or C.
• Understanding of verification methodologies and design flows.
• Strong problem-solving skills and attention to detail.
• Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.

Aufgaben

• Drive digital design activities from architecture definition through tape-out.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams to meet targets.
• Support design bring-up, integration, and tape-out activities.
• Create and maintain automation scripts, design flows, and engineering tools.
• Participate in technical reviews and continuous improvement initiatives.

Kenntnisse

RTL

ASIC/SoC/VLSI

Verilog/SystemVerilog/VHDL

Lint

CDC

Low Power

STA

CPU architectures (ARM/RISC-V/x86)

Python/Perl/C

Ausbildung

Bachelor's or Master's in Electrical/Computer Engineering

Jobbeschreibung

Capgemini Engineering is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out for high-performance, power-efficient SoCs. You will define microarchitectures, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across verification, synthesis, and physical design teams to ensure timing, power and area targets.

The role requires 6+ years in RTL/ASIC/VLSI, strong HDL skills, and experience with Lint/CDC/Low Power methodologies, STA, and CPU architectures.