DRAM Design Technology Layout Engineer Tlaquepaque, Jalisco, Mexico Posted a day ago

Micron Technology, Inc; Tlaquepaque; Híbrido; MXN 350.000 - 550.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Descripción de la vacante

Micron Technology, Inc. is seeking a DRAM Design Technology Layout Engineer to translate schematics into IP layouts for DRAM chips. You will ensure on-time delivery with quality and collaborate with global teams on layout and verification.

In this role you will apply multiple layout techniques, perform LVS/DRC/EM checks, and support area/time estimations, while guiding peers and contributing to project schedules within a fast-paced semiconductor environment.

Formación

• Bachelor's degree in Electrical/Electronics/Mechatronics or related field.
• 3+ years of experience in layout designs in advanced CMOS process.
• IP layout development and physical verification for complex designs.
• Expertise in layout area and routing optimization, yield and reliability.
• Knowledge of schematics and collaboration with CAD/circuit teams.
• Understanding layout effects on speed, capacitance, power and area.
• Strong problem-solving for area, power, performance and physical verification.
• Experience with Cadence tools including Virtuoso and Calibre.

Responsabilidades

• Responsible for Design and development of IP layouts used in DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation and execution to meet project schedule.
• Contribute to effective project-management.
• Plan and detail your layout, presenting material for global teams to review
• Optimizally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.

Conocimientos

CMOS layout

Leadership

Collaboration

Problem solving

Team communication

Educación

Bachelor’s degree in Electrical Engineering or related field

Herramientas

Cadence Virtuoso

Mentor Calibre

Device Matching

Parasitic Analysis

Descripción del empleo

Req ID:

JR101718 DRAM Design Technology Layout Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned DRAM product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution.

In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.

Responsibilities:

• Responsible for Design and development of IP layouts used in DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.
• Contribute to effective project-management.
• Plan and detail your layout, presenting material for global teams to review
• Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.

Minimum Qualifications:

• Bachelor’s degree or equivalent experience in Electrical, Electronics, Mechatronics, Robotics, Biomedical Engineering or a related field. It is necessary to have some electrical engineering background and most of those programs have them.
• Must have 3+ years of experience in layout designs in advanced CMOS process.
• Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.
• Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
• Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
• Should have adequate knowledge of schematics, collaborate with circuit designer and CAD team.
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
• Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
• Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.

Preferred Qualifications:

• Knowledge of Skill coding and layout automation is a plus.
• Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
• Should have leadership skills and able to do multi-tasking.
• AI usage (Leveraging AI, Generative AI, AI-Enabled.

"The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.