DRAM Design Layout Engineer (IP & Verification)

Micron Technology, Inc; Tlaquepaque; Híbrido; MXN 350.000 - 550.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Descripción de la vacante

Micron Technology, Inc. is seeking a DRAM Design Technology Layout Engineer to translate schematics into IP layouts for DRAM chips. You will ensure on-time delivery with quality and collaborate with global teams on layout and verification.

In this role you will apply multiple layout techniques, perform LVS/DRC/EM checks, and support area/time estimations, while guiding peers and contributing to project schedules within a fast-paced semiconductor environment.

Formación

• Bachelor's degree in Electrical/Electronics/Mechatronics or related field.
• 3+ years of experience in layout designs in advanced CMOS process.
• IP layout development and physical verification for complex designs.
• Expertise in layout area and routing optimization, yield and reliability.
• Knowledge of schematics and collaboration with CAD/circuit teams.
• Understanding layout effects on speed, capacitance, power and area.
• Strong problem-solving for area, power, performance and physical verification.
• Experience with Cadence tools including Virtuoso and Calibre.

Responsabilidades

• Responsible for Design and development of IP layouts used in DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation and execution to meet project schedule.
• Contribute to effective project-management.
• Plan and detail your layout, presenting material for global teams to review
• Optimizally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.

Conocimientos

CMOS layout

Leadership

Collaboration

Problem solving

Team communication

Educación

Bachelor’s degree in Electrical Engineering or related field

Herramientas

Cadence Virtuoso

Mentor Calibre

Device Matching

Parasitic Analysis

Descripción del empleo

Micron Technology, Inc. is seeking a DRAM Design Technology Layout Engineer to translate schematics into IP layouts for DRAM chips. You will ensure on-time delivery with quality and collaborate with global teams on layout and verification.

In this role you will apply multiple layout techniques, perform LVS/DRC/EM checks, and support area/time estimations, while guiding peers and contributing to project schedules within a fast-paced semiconductor environment.