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Micron Technology in Guadalajara, Mexico, seeks a Layout Build Engineer for its DRAM team. You will design and verify analog, mixed-signal, and block-level layouts and coordinate with global teams to meet project milestones.
The role requires deep experience with CMOS analog layout, Cadence VLE/VXL, and Calibre, plus leadership in planning and scheduling multiple layouts for high-performance memory technologies.
Micron Technology in Guadalajara, Mexico, seeks a Layout Build Engineer for its DRAM team. You will design and verify analog, mixed-signal, and block-level layouts and coordinate with global teams to meet project milestones.
The role requires deep experience with CMOS analog layout, Cadence VLE/VXL, and Calibre, plus leadership in planning and scheduling multiple layouts for high-performance memory technologies.