Lead Analog Layout Engineer – CMOS & Mixed-Signal

micron

Xalisco

Presencial

MXN 450.000 - 750.000

Jornada completa

Hace 5 días
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Descripción de la vacante

Micron Technology in Guadalajara, Mexico, seeks a Layout Build Engineer for its DRAM team. You will design and verify analog, mixed-signal, and block-level layouts and coordinate with global teams to meet project milestones.

The role requires deep experience with CMOS analog layout, Cadence VLE/VXL, and Calibre, plus leadership in planning and scheduling multiple layouts for high-performance memory technologies.

Formación

  • Approximately 5 years of analog/custom layout experience in CMOS processes across Planar/FinFET nodes.
  • BE or MTech in Electronics/VLSI or related field.
  • Expertise with Cadence VLE/VXL and Mentor Calibre DRC/LVS is required.
  • Hands-on layout of critical blocks (e.g., sensors, PLLs, ADCs, DACs, LDOs, Bandgaps).
  • Solid grasp of analog layout fundamentals and the impact on speed, power, and area.

Responsabilidades

  • Build and develop analog, mixed-signal, and custom digital blocks and support full-chip integration.
  • Perform LVS/DRC/Antenna checks, quality control, and maintain documentation.
  • Ensure timely delivery of block-level layouts with quality targets.
  • Lead planning, area/time estimation, scheduling, and task delegation across projects.
  • Collaborate with global engineering teams to ensure layout project success.

Conocimientos

Analog layout
Planar/FinFET CMOS
Cadence VLE/VXL
Mentor Calibre DRC/LVS
Block-level layout
Layout verification

Educación

BE or MTech in Electronic/VLSI

Herramientas

Cadence VLE/VXL
Mentor Calibre

Descripción del empleo

Micron Technology in Guadalajara, Mexico, seeks a Layout Build Engineer for its DRAM team. You will design and verify analog, mixed-signal, and block-level layouts and coordinate with global teams to meet project milestones.

The role requires deep experience with CMOS analog layout, Cadence VLE/VXL, and Calibre, plus leadership in planning and scheduling multiple layouts for high-performance memory technologies.

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