HBM Layout Engineer – Lead Analog/Mixed-Signal Design

Micron Technology, Inc; Tlaquepaque; Híbrido; MXN 600.000 - 900.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental & vision plans

Paid time off

Paid holidays

Descripción de la vacante

Micron Technology, Inc. in Guadalajara, Mexico is seeking a Layout Design Engineer for its HBM team to work on high-bandwidth memory projects. You will collaborate with global peers on multiple layouts, focusing on analog and custom digital blocks for AI and HPC applications.

The role requires extensive experience in CMOS layout, Cadence and Calibre tools, and strong coordination across teams to deliver high-quality layouts on schedule. This position is based in Guadalajara, Mexico.

Formación

• 5+ years of analog/custom layout design in advanced CMOS process.
• BE or MTech in Electronic/VLSI Engineering.
• Cadence VLE/VXL and Mentor Calibre DRC/LVS experience.
• Layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO.

Responsabilidades

• Design and development of analog, mixed-signal, custom digital block and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Conocimientos

Analog layout

CMOS process experience

Cadence VLE/VXL

Mentor Calibre LVS/DRC

Block layout experience

Educación

BE/MTech in Electronic/VLSI

Herramientas

Cadence tools

Mentor Calibre

Descripción del empleo

Micron Technology, Inc. in Guadalajara, Mexico is seeking a Layout Design Engineer for its HBM team to work on high-bandwidth memory projects. You will collaborate with global peers on multiple layouts, focusing on analog and custom digital blocks for AI and HPC applications.

The role requires extensive experience in CMOS layout, Cadence and Calibre tools, and strong coordination across teams to deliver high-quality layouts on schedule. This position is based in Guadalajara, Mexico.