HBM Layout Design Engineer — Analog/Mixed-Signal Expert

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.; Región Centro; Presencial; MXN 800.000 - 1.200.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. in Guadalajara, Mexico, invites an experienced Layout Design Engineer to join the HBM team, working on high-performance memory solutions and AI/HPC applications.

You will contribute to analog, mixed-signal and full-chip layouts and drive layout verification and effective integration. The role demands 5+ years of layout experience, a BE or MTech in Electronic/VLSI, and expertise with Cadence VLE/VXL and Calibre DRC/LVS.

Formación

• 5+ years of experience in analog/custom layout design in advanced CMOS process
• BE or MTech in Electronic/VLSI Engineering or related field
• Expertise with Cadence VLE/VXL and Mentor Calibre DRC/LVS is required
• Experience creating layouts for critical blocks (e.g., sensors, PLL, ADC/DAC, LDO, Bandgap)
• Knowledge of analog layout fundamentals (matching, EM, latch-up, crosstalk, IR-drop) and layout effects on speed, capacitance, power, area

Responsabilidades

• Design and development of analog, mixed-signal, and full-chip level integration support
• Perform layout verification (LVS/DRC/Antenna) and quality checks
• Ensure on-time delivery of block-level layouts with quality
• Lead planning, area/time estimation, scheduling, delegation, and execution across multiple projects
• Communicate effectively with global engineering teams to ensure project success

Conocimientos

Analog layout

Digital/mixed-signal layout

Planar/FinFET CMOS

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Project leadership

Educación

BE or MTech in Electronic/VLSI Engineering

Herramientas

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Descripción del empleo

Micron Technology, Inc. in Guadalajara, Mexico, invites an experienced Layout Design Engineer to join the HBM team, working on high-performance memory solutions and AI/HPC applications.

You will contribute to analog, mixed-signal and full-chip layouts and drive layout verification and effective integration. The role demands 5+ years of layout experience, a BE or MTech in Electronic/VLSI, and expertise with Cadence VLE/VXL and Calibre DRC/LVS.